1. Field of the Invention
The present invention relates to a system for automatically determining the logical function of a circuit, and more particularly, to a system which automatically determines the truth table of an unknown combinational logic circuit or which automatically determines the input stimuli which will cause output transitions on the outputs of a known combinational logic circuit.
2. Description of the Prior Art
When designing integrated circuits for performing particular functions, design engineers have traditionally drawn schematic diagrams of the proposed circuit setting forth all of the elements and interconnections necessary for the circuit to perform the desired functions. From the schematic diagrams, prototype circuits were built and tested. Before the advent of computer aided design (CAD) systems, the prototype of the circuit was actually built using techniques such as wire-wrapping and the like. The resulting prototype circuit was then tested by applying different combinations of input signals (input vectors) to the circuit and checking the output of the circuit on a device such as an oscilloscope. Errors in the circuit design were found when the outputs were not those desired, and the design flaw or improper connection was typically manually tracked down by careful examination of the circuit schematic and prototype wiring. Once the design flaw or improper connection was found, the prototype circuit was rebuilt and retested. This circuit design process was very time-consuming and tedious, and accordingly, design engineers sought different methods for converting the circuit schematic into a circuit which performs the desired functions.
Computer aided design (CAD) systems have greatly helped design engineers in this circuit design process. CAD systems allow the design engineer to prepare the circuit schematics on the computer, to lay out the circuit for implementation on a circuit board, and to test the circuit using logic simulation techniques. Logic simulators thus allow the design engineer to test the proposed circuit design without actually building the prototype. This is accomplished by having the design engineer specify as input to the logic simulator the elements and nodes of the circuit and the signals expected at those nodes for particular inputs. This information is determined directly from the circuit schematic diagram and is typically input into the logic simulator as an input file. The logic simulator runs this data through a model of the proposed circuit to generate the outputs of the simulated circuit. Such logic simulators are limited, however, in that they do not provide for use of a behavioral model which characterizes the circuit and thus do not allow the simulation input vectors for testing the circuit design to be automatically extracted from the circuit schematic diagram. Instead, the design engineer has had to painstakingly design and implement the simulation model and to create the input vector file.
An example of a logic simulator of the type described above is a switch-level logic simulator. Switch-level logic simulators may include node evaluation algorithms which make it possible for the logic simulator to simulate operation of circuits modeled entirely with bidirectional switches. Switch-level logic simulators are thus important tools for circuit design, for whenever a design engineer stops using classic logic gates and starts using dynamic or transfer gate logic, a switch-level logic simulator becomes necessary. This is because a conventional logic simulator cannot model all of the complex interactions which take place between non-classical transistor connections. Accordingly, the description herein is directed towards a system including a switch-level logic simulator.
A model of the circuit must be generated by the design engineer before a simulation can take place. This means that all of the elements, interconnections and nodes for a circuit design must be gathered together and converted into an input data file which is in a format acceptable to the logic simulator. Typically, the input data file contains a file having one entry for every transistor in the design (where the file may be described using node numbers) and also includes a file containing the node number to signal name mapping. The model is generated by converting the input files into a binary database which can be loaded directly into the logic simulator. In other words, the logic simulator reads the input data file and formats it into a memory based data structure that expresses the connectivity of the circuit model. This data structure is then stored as a file in the logic simulator and is referred to as the logic simulator database.
In addition to the circuit model, it is necessary to generate an input vector file of input stimuli so that operation of the circuit model can be simulated. The input vector file contains all of the desired input stimulus patterns and logic simulator control commands. The input vector file may also contain any output assertions that predict the desired behavior of the circuit model. The inclusion of the output assertions in an input vector file allows the input vector set to act as a regression test and greatly simplifies post-processing of a simulation run.
When the logic simulator is run, two output files are typically created. The first file is the simulator list file, while the second is the raw data file. The simulator list file is typically an ASCII file which lists any simulator generated status messages as well as any assertion failures. The raw data file, on the other hand, is typically a non-ASCII file which contains the node transitions for every node in the logic simulator model for all of the time steps in the simulation. The raw data files are used by the logic simulator post-processor to display any requested node for any time period. In particular, the post-processor translates the raw data file into a form which is viewable by the user. The user can preferably control which signals and which time steps are displayed.
In addition, the logic simulator may include a file which contains the values of all the nodes at a particular point in time. This file can be used to reset a simulation to a known state and is commonly used when developing an input vector file to save a state of the circuit model, such as a reset state, which can be restored over and over throughout a simulation. The ability to restart at a known point makes the process of developing an input vector file easier.
However, the development of an input vector file for testing a simulated logic design remains a quite difficult and tedious process. Typically, the input vector file is created by the design engineer by hand by specifying the input vectors necessary to excite the circuit in accordance with the truth table. In other words, the design engineer has had to specify the portions of the truth table of the circuit which were to be tested by a particular simulation and has had to prepare the necessary input file taking into account the capacitances of the circuit, propagation delays and the like so that the simulation would perform correctly. This process requires trial and error on the part of the design engineer and requires the design engineer to assume the proper simulation output response for each input stimulus. This is virtually impossible if the logic of the combinational logic circuit is unknown.
Accordingly, it is desired that the truth table and input vectors of a digital circuit to be simulated (or an unknown combinational logic circuit) be automatically determined so that the user does not have to specify the input values for testing the circuit design or determining the truth table of the circuit. Preferably, a system can be developed for automatically determining the truth table and for automatically generating a set of test vectors which excite the simulated circuit into activity without the user having to specify the inputs. The present invention has been designed to meet these needs.